As memory arrays are embedded into the microprocessors that are used in a diversity of consumer products, the trend toward portable products suggests conserving power by lowering the operating voltage of the electronic devices. However, the lowered operating voltage poses problems, especially in the dense memories, that may result in device failures. Of particular importance is the stability of the memory as the microprocessor operating voltages are lowered.
One type of memory embedded into microprocessors may be a Static Random Access Memory (SRAM) that uses a six transistor memory cell. In a conventional Complementary Metal Oxide Semiconductor (CMOS) technology the data may be written into the cross-coupled inverters through two pass transistors. In a read operation, the data from the accessed memory cell may be transferred through the pass transistors to bit lines and differentially detected by a sense amp circuit. When the operating voltage of the microprocessor is lowered to conserve power, the data stored by the memory cell may be changed by a read operation if the memory cell becomes unstable at the lower voltages.
Thus, there is a continuing need for better ways to provide flexibility for operating the microprocessor or other digital circuits at a desired lower voltage while preserving the stability of the embedded memory.